RTLDoc datamover (lkesting/konark) - RTLDoc example
module

stream_register

common_cells.bender/git/checkouts/common_cells-2ee00d692a2e59d4/src/stream_register.sv:16elaboratedas datamover_top_wrap.i_datamover_top.i_engine.gen_im2col.i_im2col.i_out_reg
7in
3out
0sub

Register with a simple stream-like ready/valid handshake. This register does not cut combinatorial paths on all control signals; if you need a complete cut, use the spill_register.

Interface

the boundary of stream_register — it instantiates no other module
G m__stream_register stream_register p__ready_o ready_o m__stream_register->p__ready_o p__valid_o valid_o m__stream_register->p__valid_o p__data_o data_o m__stream_register->p__data_o p__valid_i valid_i p__valid_i->m__stream_register p__data_i data_i p__data_i->m__stream_register p__ready_i ready_i p__ready_i->m__stream_register
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The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Clocks

clk_i

Resets

rst_niactive-low

Clears

clr_isynchronous

Test / DFT

testmode_i

Ports 10

Inputs 7

DirNameTypeWidth
in clk_i logic 1
in rst_ni logic 1
in clr_i logic 1
in testmode_i logic 1
in valid_i logic 1
in data_i stream_register.T 512
in ready_i logic 1

Outputs 3

DirNameTypeWidth
out ready_o logic 1
out valid_o logic 1
out data_o stream_register.T 512

Parameters 1

NameResolved value
T-

Instantiated by