interface
hwpe_ctrl_intf_periph
1in
0out
0sub
Signals 10
the wires that the two sides of this interface share
| Name | Type | Width |
|---|---|---|
| req | logic | 1 |
| gnt | logic | 1 |
| add | logic[31:0] | 32 |
| wen | logic | 1 |
| be | logic[3:0] | 4 |
| data | logic[31:0] | 32 |
| id | logic[9:0] | 10 |
| r_data | logic[31:0] | 32 |
| r_valid | logic | 1 |
| r_id | logic[9:0] | 10 |
Modports 2
each side of the interface, with the direction of each signal from that side
| Modport | Drives | Reads |
|---|---|---|
| master | req, add, wen, be, data, id | gnt, r_data, r_valid, r_id |
| slave | gnt, r_data, r_valid, r_id | req, add, wen, be, data, id |
Clocks
clk
Ports 1
Inputs 1
| Dir | Name | Type | Width |
|---|---|---|---|
| in | clk | logic | 1 |
Parameters 1
| Name | Resolved value |
|---|---|
| ID_WIDTH | 32'd10 |
Imports
hwpe_ctrl_package::*