module
hci_core_assign
1in
1out
0sub
The hci_core_assign module implements a simple assignment for
HCI-Core streams.
Interface
the boundary of hci_core_assign — it instantiates no other moduleThe ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.
Ports 2
Inputs 1
| Dir | Name | Type | Width |
|---|---|---|---|
| in | tcdm_target | hci_core_intf .target | - |
Outputs 1
| Dir | Name | Type | Width |
|---|---|---|---|
| out | tcdm_initiator | hci_core_intf .initiator | - |
Instantiated by
Imports
hwpe_stream_package::*