hci_core_sink
The hci_core_sink module is the high-level sink streamer
performing a series of stores on a HCI-Core interface
from an incoming HWPE-Stream data stream from a HWPE engine/datapath.
The sink streamer is a composite module that makes use of many other
fundamental IPs.
Fundamentally, a sink streamer acts as a specialized DMA engine acting out a predefined pattern from an hwpe_stream_addressgen_v3 to perform a burst of stores via a HCI-Core interface, consuming a HWPE-Stream data stream into the HCI-Core data field. The sink streamer is insensitive to memory latency. This is due to the nature of store streams, which are unidirectional (i.e. addr and data move in the same direction).
Misaligned accesses are supported by widening the HCI-Core data width of 32 bits compared to the HWPE-Stream that gets consumed by the streamer. The stream is shifted according to the address alignment and invalid bytes are disabled by unsetting their strb. This feature can be deactivated by unsetting the MISALIGNED_ACCESS parameter; in this case, the sink will only work correctly if all data is aligned to a word boundary.
Name |
Default |
Description |
TCDM_FIFO_DEPTH |
2 |
If >0, the module produces a HWPE-MemDecoupled interface and includes a TCDM FIFO of this depth. |
TRANS_CNT |
16 |
Number of bits supported in the transaction counter of the address generator, which will overflow at 2^ TRANS_CNT. |
MISALIGNED_ACCESS |
1 |
If set to 0, the sink will not support non-word-aligned HWPE-Mem accesses. |
Name |
Type |
Description |
req_start |
logic |
When 1, the sink streamer operation is started if it is ready. |
addressgen_ctrl |
ctrl_addressgen_v3_t |
Configuration of the address generator (see hwpe_stream_addresgen_v3). |
Name |
Type |
Description |
ready_start |
logic |
1 when the sink streamer is ready to start operation, from the first IDLE state cycle on. |
done |
logic |
1 for one cycle when the streamer ends operation, in the cycle before it goes to IDLE state . |
addressgen_flags |
flags_addressgen_v3_t |
Address generator flags (see hwpe_stream_addresgen_v3). |
Internal connectivity
the submodules of hci_core_sink and the signals between themThe ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.
Clocks
Resets
Clears
Test / DFT
Ports 9
Inputs 7
| Dir | Name | Type | Width |
|---|---|---|---|
| in | clk_i | logic | 1 |
| in | rst_ni | logic | 1 |
| in | test_mode_i | logic | 1 |
| in | clear_i | logic | 1 |
| in | enable_i ctrl | logic | 1 |
| in | stream | hwpe_stream_intf_stream .sink | - |
| in | ctrl_i ctrl | hci_package::hci_streamer_ctrl_t | 653 |
Outputs 2
| Dir | Name | Type | Width |
|---|---|---|---|
| out | tcdm | hci_core_intf .initiator | - |
| out | flags_o flag | hci_package::hci_streamer_flags_t | 4 |
Parameters 15
| Name | Resolved value |
|---|---|
| TCDM_FIFO_DEPTH | 32'd0 |
| TRANS_CNT | 32'd24 |
| MISALIGNED_ACCESSES | 32'd1 |
| ELEMENT_WIDTH | 32'd8 |
| ELEMENTS_PER_BANK | 32'd8 |
| BANK_DATA_WIDTH | 32'd64 |
| ELEMENT_INDEX_WIDTH | 32'd3 |
| DIM_ENABLE_1H | 4'b1111 |
| STRIDE_LAST_1H | 4'b0 |
| LEN_LAST_1H | 4'b0 |
| ALTERNATE_1H | 4'b0 |
| ALT_SKIP_1H | 4'b0 |
| HCI_SIZE_tcdm | 224'd36156105996294961723667258600855805061...e23 |
| DATA_WIDTH | 32'd576 |
| EHW | 32'd1 |
Submodules 3
| Instance | Module | Count | Conns |
|---|---|---|---|
| i_addressgen | hwpe_stream_addressgen_v4 | 1 | 8 |
| i_fifo_addr | hwpe_stream_fifo | 1 | 6 |
| i_tcdm_assign | hci_core_assign | 1 | 2 |