hci_core_sink · RTLDoc

The hci_core_sink module is the high-level sink streamer performing a series of stores on a HCI-Core interface from an incoming HWPE-Stream data stream from a HWPE engine/datapath. The sink streamer is a composite module that makes use of many other fundamental IPs.

Fundamentally, a sink streamer acts as a specialized DMA engine acting out a predefined pattern from an hwpe_stream_addressgen_v3 to perform a burst of stores via a HCI-Core interface, consuming a HWPE-Stream data stream into the HCI-Core data field. The sink streamer is insensitive to memory latency. This is due to the nature of store streams, which are unidirectional (i.e. addr and data move in the same direction).

Misaligned accesses are supported by widening the HCI-Core data width of 32 bits compared to the HWPE-Stream that gets consumed by the streamer. The stream is shifted according to the address alignment and invalid bytes are disabled by unsetting their strb. This feature can be deactivated by unsetting the MISALIGNED_ACCESS parameter; in this case, the sink will only work correctly if all data is aligned to a word boundary.

`hci_core_sink` design-time parameters.
Name	Default	Description
TCDM_FIFO_DEPTH	2	If >0, the module produces a HWPE-MemDecoupled interface and includes a TCDM FIFO of this depth.
TRANS_CNT	16	Number of bits supported in the transaction counter of the address generator, which will overflow at 2^ TRANS_CNT.
MISALIGNED_ACCESS	1	If set to 0, the sink will not support non-word-aligned HWPE-Mem accesses.

`hci_core_sink` input control signals.
Name	Type	Description
req_start	logic	When 1, the sink streamer operation is started if it is ready.
addressgen_ctrl	ctrl_addressgen_v3_t	Configuration of the address generator (see hwpe_stream_addresgen_v3).

`hci_core_sink` output flags.
Name	Type	Description
ready_start	logic	1 when the sink streamer is ready to start operation, from the first IDLE state cycle on.
done	logic	1 for one cycle when the streamer ends operation, in the cycle before it goes to IDLE state .
addressgen_flags	flags_addressgen_v3_t	Address generator flags (see hwpe_stream_addresgen_v3).

Internal connectivity

the submodules of hci_core_sink and the signals between them

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Blue: an input. Magenta: an output. Green: an interface. Orange: no direction. A hexagon shows a port that goes in two directions. The clock and the reset nets are not in the graph.

Clocks

clk_i

Resets

rst_niactive-low

Ports 9

Inputs 7

Dir	Name	Type	Width
in	clk_i	logic	1
in	rst_ni	logic	1
in	test_mode_i	logic	1
in	clear_i	logic	1
in	enable_i	logic	1
in	stream	hwpe_stream_intf_stream .sink	-
in	ctrl_i	hci_package::hci_streamer_ctrl_t	453

Outputs 2

Dir	Name	Type	Width
out	tcdm	hci_core_intf .initiator	-
out	flags_o	hci_package::hci_streamer_flags_t	4

Parameters 12

Name	Resolved value
TCDM_FIFO_DEPTH	32'd0
TRANS_CNT	32'd16
MISALIGNED_ACCESSES	32'd1
ELEMENT_WIDTH	32'd8
ELEMENTS_PER_BANK	32'd4
BANK_DATA_WIDTH	32'd32
ELEMENT_INDEX_WIDTH	32'd2
DIM_ENABLE_1H	4'b1111
PARTIAL_TILING	32'd0
HCI_SIZE_tcdm	224'h0
DATA_WIDTH	32'd0
EHW	32'd0

Submodules 3

Instance	Module	Count	Conns
i_addressgen	hwpe_stream_addressgen_v4	1	8
i_fifo_addr	hwpe_stream_fifo	1	6
i_tcdm_assign	hci_core_assign	1	2

Interfaces / streams 3

addr_pushhwpe_stream_intf_stream addr_pophwpe_stream_intf_stream tcdm_targethci_core_intf

Instantiated by

datamover_streamer

Imports

hwpe_stream_package::*hci_package::*