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module

datamover_ctrl

datamover rtl/ctrl/datamover_ctrl.sv:24 elaboratedas datamover_top_wrap.i_datamover_top.i_ctrl
4in
5out
2sub

Internal connectivity

the submodules of datamover_ctrl and the signals between them
G cluster_datamover_ctrl datamover_ctrl p__flags_streamer_i flags_streamer_i i__i_target i_target hwpe_ctrl_target i__i_regif i_regif datamover_regif l__logic internal logic of datamover_ctrl n__hwif_in hwif_in n__hwif_out hwif_out n__job_done_d job_done_d n__job_status job_status n__job_trigger job_trigger n__target_cpuif_addr target_cpuif_addr n__target_cpuif_rd_ack target_cpuif_rd_ack n__target_cpuif_rd_data target_cpuif_rd_data n__target_cpuif_rd_err target_cpuif_rd_err n__target_cpuif_req target_cpuif_req n__target_cpuif_req_is_wr target_cpuif_req_is_wr n__target_cpuif_req_stall_rd target_cpuif_req_stall_rd n__target_cpuif_req_stall_wr target_cpuif_req_stall_wr n__target_cpuif_wr_ack target_cpuif_wr_ack n__target_cpuif_wr_biten target_cpuif_wr_biten n__target_cpuif_wr_data target_cpuif_wr_data n__target_cpuif_wr_err target_cpuif_wr_err p__periph periph p__flags_streamer_i->l__logic p__periph->i__i_target slave p__busy_o busy_o p__ctrl_engine_o ctrl_engine_o p__ctrl_streamer_o ctrl_streamer_o p__evt_o evt_o i__i_target->n__hwif_in i__i_target->n__job_trigger i__i_target->n__target_cpuif_addr i__i_target->n__target_cpuif_req i__i_target->n__target_cpuif_req_is_wr i__i_target->n__target_cpuif_wr_biten i__i_target->n__target_cpuif_wr_data i__i_regif->n__hwif_out i__i_regif->n__target_cpuif_rd_ack i__i_regif->n__target_cpuif_rd_data i__i_regif->n__target_cpuif_rd_err i__i_regif->n__target_cpuif_req_stall_rd i__i_regif->n__target_cpuif_req_stall_wr i__i_regif->n__target_cpuif_wr_ack i__i_regif->n__target_cpuif_wr_err l__logic->p__busy_o l__logic->p__ctrl_engine_o l__logic->p__ctrl_streamer_o l__logic->p__evt_o l__logic->n__job_done_d l__logic->n__job_status n__hwif_in->i__i_regif n__hwif_out->i__i_target n__job_done_d->i__i_target n__job_status->i__i_target n__job_trigger->l__logic n__target_cpuif_addr->i__i_regif n__target_cpuif_rd_ack->i__i_target n__target_cpuif_rd_data->i__i_target n__target_cpuif_rd_err->i__i_target n__target_cpuif_req->i__i_regif n__target_cpuif_req_is_wr->i__i_regif n__target_cpuif_req_stall_rd->i__i_target n__target_cpuif_req_stall_wr->i__i_target n__target_cpuif_wr_ack->i__i_target n__target_cpuif_wr_biten->i__i_regif n__target_cpuif_wr_data->i__i_regif n__target_cpuif_wr_err->i__i_target
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The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Clocks

clk_i

Resets

rst_niactive-low

Clears

clear_osynchronous

Ports 9

Inputs 4

DirNameTypeWidth
in clk_i logic 1
in rst_ni logic 1
in flags_streamer_i flag datamover_package::flags_streamer_t 9
in periph hwpe_ctrl_intf_periph .slave -

Outputs 5

DirNameTypeWidth
out evt_o flag logic[7:0][1:0] 16
out busy_o flag logic 1
out clear_o logic 1
out ctrl_streamer_o ctrl datamover_package::ctrl_streamer_t 1306
out ctrl_engine_o ctrl datamover_package::ctrl_engine_t 88

Parameters 5

NameResolved value
NUM_CORES32'd8
NUM_CONTEXT32'd2
ID_WIDTH32'd10
REGFILE_N_EVT32'd2
TRANSP_LEN32'd64

Submodules 2

InstanceModuleCountConns
i_target hwpe_ctrl_target 1 24
i_regif datamover_regif 1 16

Instantiated by

datamover_top

Imports

datamover_package::*datamover_regif_pkg::*hwpe_ctrl_package::*hci_package::*