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module

datamover_ctrl

datamover rtl/ctrl/datamover_ctrl.sv:24 elaborated
4in
5out
2sub

Internal connectivity

the submodules of datamover_ctrl and the signals between them
G cluster_datamover_ctrl datamover_ctrl p__periph periph i__i_target i_target hwpe_ctrl_target p__periph->i__i_target n__hwif_in hwif_in i__i_target->n__hwif_in n__target_cpuif_addr target_cpuif_addr i__i_target->n__target_cpuif_addr n__target_cpuif_req target_cpuif_req i__i_target->n__target_cpuif_req n__target_cpuif_req_is_wr target_cpuif_req_is_wr i__i_target->n__target_cpuif_req_is_wr n__target_cpuif_wr_biten target_cpuif_wr_biten i__i_target->n__target_cpuif_wr_biten n__target_cpuif_wr_data target_cpuif_wr_data i__i_target->n__target_cpuif_wr_data i__i_regif i_regif datamover_regif n__hwif_out hwif_out i__i_regif->n__hwif_out n__target_cpuif_rd_ack target_cpuif_rd_ack i__i_regif->n__target_cpuif_rd_ack n__target_cpuif_rd_data target_cpuif_rd_data i__i_regif->n__target_cpuif_rd_data n__target_cpuif_rd_err target_cpuif_rd_err i__i_regif->n__target_cpuif_rd_err n__target_cpuif_req_stall_rd target_cpuif_req_stall_rd i__i_regif->n__target_cpuif_req_stall_rd n__target_cpuif_req_stall_wr target_cpuif_req_stall_wr i__i_regif->n__target_cpuif_req_stall_wr n__target_cpuif_wr_ack target_cpuif_wr_ack i__i_regif->n__target_cpuif_wr_ack n__target_cpuif_wr_err target_cpuif_wr_err i__i_regif->n__target_cpuif_wr_err n__hwif_in->i__i_regif n__hwif_out->i__i_target n__target_cpuif_addr->i__i_regif n__target_cpuif_rd_ack->i__i_target n__target_cpuif_rd_data->i__i_target n__target_cpuif_rd_err->i__i_target n__target_cpuif_req->i__i_regif n__target_cpuif_req_is_wr->i__i_regif n__target_cpuif_req_stall_rd->i__i_target n__target_cpuif_req_stall_wr->i__i_target n__target_cpuif_wr_ack->i__i_target n__target_cpuif_wr_biten->i__i_regif n__target_cpuif_wr_data->i__i_regif n__target_cpuif_wr_err->i__i_target
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Blue: an input. Magenta: an output. Green: an interface. Orange: no direction. A hexagon shows a port that goes in two directions. The clock and the reset nets are not in the graph.

Clocks

clk_i

Resets

rst_niactive-low

Ports 9

Inputs 4

DirNameTypeWidth
in clk_i logic 1
in rst_ni logic 1
in flags_streamer_i datamover_package::flags_streamer_t 9
in periph hwpe_ctrl_intf_periph .slave -

Outputs 5

DirNameTypeWidth
out evt_o logic[1:0][1:0] 4
out busy_o logic 1
out clear_o logic 1
out ctrl_streamer_o datamover_package::ctrl_streamer_t 906
out ctrl_engine_o datamover_package::ctrl_engine_t 97

Parameters 5

NameResolved value
NUM_CORES32'd2
NUM_CONTEXT32'd2
ID_WIDTH32'd4
REGFILE_N_EVT32'd2
TRANSP_LEN32'd64

Submodules 2

InstanceModuleCountConns
i_target hwpe_ctrl_target 1 24
i_regif datamover_regif 1 16

Instantiated by

datamover_top

Imports

datamover_package::*datamover_regif_pkg::*hwpe_ctrl_package::*hci_package::*