hci_core_source

The hci_core_source module is the high-level source streamer performing a series of loads on a HCI-Core interface and producing a HWPE-Stream data stream to feed a HWPE engine/datapath. The source streamer is a composite module that makes use of many other fundamental IPs.

Fundamentally, a source streamer acts as a specialized DMA engine acting out a predefined pattern from an hwpe_stream_addressgen_v3 to perform a burst of loads via a HCI-Core interface, producing a HWPE-Stream data stream from the HCI-Core r_data field. By default, the HCI-Core streamer supports delayed accesses using a HCI-Core interface.

Misaligned accesses are supported by widening the HCI-Core data width of 32 bits compared to the HWPE-Stream that gets produced by the streamer. Unused bytes are simply ignored. This feature can be deactivated by unsetting the MISALIGNED_ACCESS parameter; in this case, the sink will only work correctly if all data is aligned to a word boundary.

In principle, the source streamer is insensitive to latency. However, when configured to support misaligned memory accesses, the address FIFO depth sets the maximum supported latency. This parameter can be controlled by the ADDR_MIS_DEPTH parameter (default 8).

`hci_core_source` design-time parameters.
Name	Default	Description
LATCH_FIFO	0	If 1, use latches instead of flip-flops (requires special constraints in synthesis).
TRANS_CNT	16	Number of bits supported in the transaction counter of the address generator, which will overflow at 2^ TRANS_CNT.
ADDR_MIS_DEPTH	8	Depth of the misaligned address FIFO. This must be equal to the max-latency between the HCI-Core gnt and r_valid.
MISALIGNED_ACCESS	1	If set to 0, the source will not support non-word-aligned HCI-Core accesses.
PASSTHROUGH_FIFO	0	If set to 1, the address FIFO will be capable of fall-through operation (i.e., skipping the FIFO latency entirely).
TCDM_R_READY_SUPPORT	1	If 0, the TCDM ignores r_ready; the source self-limits to one outstanding load instead of backpressuring responses.
STRIDE_LAST_1H	4'b0000	Bit N: give dimension N a second stride, used at the last index of another one (see `hwpe_stream_addressgen_v4`).
LEN_LAST_1H	4'b0000	Bit N: give dimension N a second length, used at the last index of an outer one (short trailing tile).
ALTERNATE_1H	4'b0000	Bit N: let dimension N sweep up and down instead of always up.
ALT_SKIP_1H	4'b0000	Bit N: let dimension N skip the shared element at a sweep turnaround.

`hci_core_source` input control signals.
Name	Type	Description
req_start	logic	When 1, the source streamer operation is started if it is ready.
addressgen_ctrl	ctrl_addressgen_v3_t	Configuration of the address generator (see hwpe_stream_addresgen_v3).

`hci_core_source` output flags.
Name	Type	Description
ready_start	logic	1 when the source streamer is ready to start operation, from the first IDLE state cycle on.
done	logic	1 for one cycle when the streamer ends operation, in the cycle before it goes to IDLE state .
addressgen_flags	flags_addressgen_v3_t	Address generator flags (see hwpe_stream_addresgen_v3).

Internal connectivity

the submodules of hci_core_source and the signals between them

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The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Clocks

clk_i

Resets

rst_niactive-low

Clears

clear_isynchronous

Test / DFT

test_mode_i

Ports 9

Inputs 6

Dir	Name	Type	Width
in	clk_i	logic	1
in	rst_ni	logic	1
in	test_mode_i	logic	1
in	clear_i	logic	1
in	enable_i ctrl	logic	1
in	ctrl_i ctrl	hci_package::hci_streamer_ctrl_t	653

Outputs 3

Dir	Name	Type	Width
out	tcdm	hci_core_intf .initiator	-
out	stream	hwpe_stream_intf_stream .source	-
out	flags_o flag	hci_package::hci_streamer_flags_t	4

Parameters 20

Name	Resolved value
LATCH_FIFO	32'd0
TRANS_CNT	32'd24
ADDR_MIS_DEPTH	32'd8
MISALIGNED_ACCESSES	32'd1
PASSTHROUGH_FIFO	32'd0
TCDM_R_READY_SUPPORT	1'b0
ELEMENT_WIDTH	32'd8
ELEMENTS_PER_BANK	32'd8
BANK_DATA_WIDTH	32'd64
ADDR_OFFSET	32'd3
DIM_ENABLE_1H	4'b1111
STRIDE_LAST_1H	4'b0
LEN_LAST_1H	4'b0
ALTERNATE_1H	4'b0
ALT_SKIP_1H	4'b0
HCI_SIZE_tcdm	224'd36156105996294961723667258600855805061...e23
DATA_WIDTH	32'd576
EHW	32'd1
STREAM_MISALIGNED_DW	32'd512
ADDR_OFFSET_BYTE	32'd8

Submodules 3

Instance	Module	Count	Conns
i_addressgen	hwpe_stream_addressgen_v4	1	8
i_fifo_addr	hwpe_stream_fifo	1	6
i_addr_misaligned_fifo	hwpe_stream_fifo	1	6

Interfaces / streams 4

addr_pushhwpe_stream_intf_stream addr_pophwpe_stream_intf_stream addr_misaligned_pushhwpe_stream_intf_stream addr_misaligned_pophwpe_stream_intf_stream

Instantiated by

datamover_streamer

Imports

hwpe_stream_package::*hci_package::*