interface
hwpe_stream_intf_stream
1in
0out
0sub
hwpe_stream_intf_tcdm
Signals 4
the wires that the two sides of this interface share
| Name | Type | Width |
|---|---|---|
| valid | logic | 1 |
| ready | logic | 1 |
| data | logic[511:0] | 512 |
| strb | logic[63:0] | 64 |
Modports 3
each side of the interface, with the direction of each signal from that side
| Modport | Drives | Reads |
|---|---|---|
| source | valid, data, strb | ready |
| sink | ready | valid, data, strb |
| monitor | valid, data, strb, ready |
Clocks
clk
Ports 1
Inputs 1
| Dir | Name | Type | Width |
|---|---|---|---|
| in | clk | logic | 1 |
Parameters 5
| Name | Resolved value |
|---|---|
| DATA_WIDTH | 32'd512 |
| ELEMENT_WIDTH | 32'd8 |
| STRB_WIDTH | 32'd64 |
| BYPASS_VCR_ASSERT | 1'b0 |
| BYPASS_VDR_ASSERT | 1'b0 |
Imports
hwpe_stream_package::*