hwpe_ctrl_target
The hwpe_ctrl_target module implements the control-side target (slave)
port of an HWPE, exposing a hwpe_ctrl_intf_periph interface used by an
external core to program a memory-mapped register file. It supersedes the
deprecated hwpe_ctrl_slave module: rather than hard-coding a register
file, it relies on a register interface that is generated out of a
SystemRDL description. The hwpe-ctrl repository ships a reference
hwpe_ctrl_regif_example.rdl description and a rdl.sh helper script
that invokes PeakRDL to generate the register interface; HWPEs must
internalize this description and modify its contents to match their own
set of job-independent and job-dependent registers (without altering
the mandatory registers, see below).
Then, the hwpe_ctrl_target can be integrated by 1) overriding the
parametric types hwpe_ctrl_regif_in_t, hwpe_ctrl_regif_out_t,
hwpe_ctrl_job_indep_t, hwpe_ctrl_job_dep_t with the ones produced by
PeakRDL; 2) plugging the register-interface (cpuif) signals to the
SystemRDL-generated register interface block; 3) plugging hwif_in and
hwif_out to the same block.
The module also implements an internal job queue (of depth NB_CONTEXT) that allows new jobs to be enqueued via the ACQUIRE / COMMIT_TRIGGER mandatory registers while the HWPE is still busy executing the previous one. The mandatory registers (always present in the SystemRDL description) are summarized below.
Internal connectivity
the submodules of hwpe_ctrl_target and the signals between themBlue: an input. Magenta: an output. Green: an interface. Orange: no direction. A hexagon shows a port that goes in two directions. The clock and the reset nets are not in the graph.
Clocks
Resets
Ports 24
Inputs 13
| Dir | Name | Type | Width |
|---|---|---|---|
| in | clk_i | logic | 1 |
| in | rst_ni | logic | 1 |
| in | target | hwpe_ctrl_intf_periph .slave | - |
| in | job_done_i | logic | 1 |
| in | job_status_i | logic[31:0] | 32 |
| in | target_cpuif_req_stall_wr_i | logic | 1 |
| in | target_cpuif_req_stall_rd_i | logic | 1 |
| in | target_cpuif_rd_ack_i | logic | 1 |
| in | target_cpuif_rd_err_i | logic | 1 |
| in | target_cpuif_rd_data_i | logic[31:0] | 32 |
| in | target_cpuif_wr_ack_i | logic | 1 |
| in | target_cpuif_wr_err_i | logic | 1 |
| in | hwif_out | hwpe_ctrl_target.hwpe_ctrl_regif_out_t | 763 |
Outputs 11
| Dir | Name | Type | Width |
|---|---|---|---|
| out | clear_o | logic | 1 |
| out | job_trigger_o | logic | 1 |
| out | job_indep_regs_o | hwpe_ctrl_target.hwpe_ctrl_job_indep_t | 32 |
| out | job_dep_regs_valid_o | logic | 1 |
| out | job_dep_regs_o | hwpe_ctrl_target.hwpe_ctrl_job_dep_t | 544 |
| out | target_cpuif_req_o | logic | 1 |
| out | target_cpuif_req_is_wr_o | logic | 1 |
| out | target_cpuif_addr_o | logic[31:0] | 32 |
| out | target_cpuif_wr_data_o | logic[31:0] | 32 |
| out | target_cpuif_wr_biten_o | logic[31:0] | 32 |
| out | hwif_in | hwpe_ctrl_target.hwpe_ctrl_regif_in_t | 72 |
Parameters 11
| Name | Resolved value |
|---|---|
| NB_CONTEXT | 32'd2 |
| NB_CLEAR_CYCLES | 32'd3 |
| ID_WIDTH | 32'd4 |
| ADDR_WIDTH | 32'd10 |
| AUTOTRIGGER_WAIT_CYCLES | 32'd3 |
| hwpe_ctrl_regif_in_t | - |
| hwpe_ctrl_regif_out_t | - |
| hwpe_ctrl_job_indep_t | - |
| hwpe_ctrl_job_dep_t | - |
| HWPE_CTRL_JOB_QUEUE_FULL_ERR_CODE | 32'd4294967295 |
| HWPE_CTRL_JOB_ACQUIRED_ERR_CODE | 32'd4294967294 |
Submodules 1
| Instance | Module | Count | Conns |
|---|---|---|---|
| i_job_fifo | fifo_v3 | 1 | 11 |