RTLDoc datamover (lkesting/konark) - RTLDoc example
module

hwpe_ctrl_target

hwpe-ctrl.bender/git/checkouts/hwpe-ctrl-7551e0694e9ad506/rtl/hwpe_ctrl_target.sv:89elaborated
13in
11out
1sub

The hwpe_ctrl_target module implements the control-side target (slave) port of an HWPE, exposing a hwpe_ctrl_intf_periph interface used by an external core to program a memory-mapped register file. It supersedes the deprecated hwpe_ctrl_slave module: rather than hard-coding a register file, it relies on a register interface that is generated out of a SystemRDL description. The hwpe-ctrl repository ships a reference hwpe_ctrl_regif_example.rdl description and a rdl.sh helper script that invokes PeakRDL to generate the register interface; HWPEs must internalize this description and modify its contents to match their own set of job-independent and job-dependent registers (without altering the mandatory registers, see below).

Then, the hwpe_ctrl_target can be integrated by 1) overriding the parametric types hwpe_ctrl_regif_in_t, hwpe_ctrl_regif_out_t, hwpe_ctrl_job_indep_t, hwpe_ctrl_job_dep_t with the ones produced by PeakRDL; 2) plugging the register-interface (cpuif) signals to the SystemRDL-generated register interface block; 3) plugging hwif_in and hwif_out to the same block.

The module also implements an internal job queue (of depth NB_CONTEXT) that allows new jobs to be enqueued via the ACQUIRE / COMMIT_TRIGGER mandatory registers while the HWPE is still busy executing the previous one. The mandatory registers (always present in the SystemRDL description) are summarized below.

Internal connectivity

the submodules of hwpe_ctrl_target and the signals between them
G cluster_hwpe_ctrl_target hwpe_ctrl_target p__hwif_out hwif_out i__i_job_fifo i_job_fifo fifo_v3 p__hwif_out->i__i_job_fifo p__job_dep_regs_o job_dep_regs_o p__job_done_i job_done_i p__job_done_i->i__i_job_fifo i__i_job_fifo->p__job_dep_regs_o
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Blue: an input. Magenta: an output. Green: an interface. Orange: no direction. A hexagon shows a port that goes in two directions. The clock and the reset nets are not in the graph.

Clocks

clk_i

Resets

rst_niactive-low

Ports 24

Inputs 13

DirNameTypeWidth
in clk_i logic 1
in rst_ni logic 1
in target hwpe_ctrl_intf_periph .slave -
in job_done_i logic 1
in job_status_i logic[31:0] 32
in target_cpuif_req_stall_wr_i logic 1
in target_cpuif_req_stall_rd_i logic 1
in target_cpuif_rd_ack_i logic 1
in target_cpuif_rd_err_i logic 1
in target_cpuif_rd_data_i logic[31:0] 32
in target_cpuif_wr_ack_i logic 1
in target_cpuif_wr_err_i logic 1
in hwif_out hwpe_ctrl_target.hwpe_ctrl_regif_out_t 763

Outputs 11

DirNameTypeWidth
out clear_o logic 1
out job_trigger_o logic 1
out job_indep_regs_o hwpe_ctrl_target.hwpe_ctrl_job_indep_t 32
out job_dep_regs_valid_o logic 1
out job_dep_regs_o hwpe_ctrl_target.hwpe_ctrl_job_dep_t 544
out target_cpuif_req_o logic 1
out target_cpuif_req_is_wr_o logic 1
out target_cpuif_addr_o logic[31:0] 32
out target_cpuif_wr_data_o logic[31:0] 32
out target_cpuif_wr_biten_o logic[31:0] 32
out hwif_in hwpe_ctrl_target.hwpe_ctrl_regif_in_t 72

Parameters 11

NameResolved value
NB_CONTEXT32'd2
NB_CLEAR_CYCLES32'd3
ID_WIDTH32'd4
ADDR_WIDTH32'd10
AUTOTRIGGER_WAIT_CYCLES32'd3
hwpe_ctrl_regif_in_t-
hwpe_ctrl_regif_out_t-
hwpe_ctrl_job_indep_t-
hwpe_ctrl_job_dep_t-
HWPE_CTRL_JOB_QUEUE_FULL_ERR_CODE32'd4294967295
HWPE_CTRL_JOB_ACQUIRED_ERR_CODE32'd4294967294

Submodules 1

InstanceModuleCountConns
i_job_fifo fifo_v3 1 11

Instantiated by

Imports

hwpe_ctrl_package::*