module

datamover_regif

8in

8out

0sub

Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator https://github.com/SystemRDL/PeakRDL-regblock

This module instantiates no other module.

Clocks

clk

arst_nactive-low

Dir	Name	Type	Width
in	clk	logic	1
in	arst_n	logic	1
in	s_cpuif_req	logic	1
in	s_cpuif_req_is_wr	logic	1
in	s_cpuif_addr	logic[31:0]	32
in	s_cpuif_wr_data	logic[31:0]	32
in	s_cpuif_wr_biten	logic[31:0]	32
in	hwif_in	datamover_regif_pkg::datamover_regif__in_t	72

Dir	Name	Type	Width
out	s_cpuif_req_stall_wr	logic	1
out	s_cpuif_req_stall_rd	logic	1
out	s_cpuif_rd_ack	logic	1
out	s_cpuif_rd_err	logic	1
out	s_cpuif_rd_data	logic[31:0]	32
out	s_cpuif_wr_ack	logic	1
out	s_cpuif_wr_err	logic	1
out	hwif_out	datamover_regif_pkg::datamover_regif__out_t	763