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module

datamover_regif

datamover rtl/ctrl/regif/datamover_regif.sv:4 elaboratedas datamover_top_wrap.i_datamover_top.i_ctrl.i_regif
8in
8out
0sub

Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator https://github.com/SystemRDL/PeakRDL-regblock

Interface

the boundary of datamover_regif — it instantiates no other module
G m__datamover_regif datamover_regif p__s_cpuif_req_stall_wr s_cpuif_req_stall_wr m__datamover_regif->p__s_cpuif_req_stall_wr p__s_cpuif_req_stall_rd s_cpuif_req_stall_rd m__datamover_regif->p__s_cpuif_req_stall_rd p__s_cpuif_rd_ack s_cpuif_rd_ack m__datamover_regif->p__s_cpuif_rd_ack p__s_cpuif_rd_err s_cpuif_rd_err m__datamover_regif->p__s_cpuif_rd_err p__s_cpuif_rd_data s_cpuif_rd_data m__datamover_regif->p__s_cpuif_rd_data p__s_cpuif_wr_ack s_cpuif_wr_ack m__datamover_regif->p__s_cpuif_wr_ack p__s_cpuif_wr_err s_cpuif_wr_err m__datamover_regif->p__s_cpuif_wr_err p__hwif_out hwif_out m__datamover_regif->p__hwif_out p__s_cpuif_req s_cpuif_req p__s_cpuif_req->m__datamover_regif p__s_cpuif_req_is_wr s_cpuif_req_is_wr p__s_cpuif_req_is_wr->m__datamover_regif p__s_cpuif_addr s_cpuif_addr p__s_cpuif_addr->m__datamover_regif p__s_cpuif_wr_data s_cpuif_wr_data p__s_cpuif_wr_data->m__datamover_regif p__s_cpuif_wr_biten s_cpuif_wr_biten p__s_cpuif_wr_biten->m__datamover_regif p__hwif_in hwif_in p__hwif_in->m__datamover_regif
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The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Clocks

clk

Resets

arst_nactive-low

Ports 16

Inputs 8

DirNameTypeWidth
in clk logic 1
in arst_n logic 1
in s_cpuif_req logic 1
in s_cpuif_req_is_wr logic 1
in s_cpuif_addr logic[31:0] 32
in s_cpuif_wr_data logic[31:0] 32
in s_cpuif_wr_biten logic[31:0] 32
in hwif_in datamover_regif_pkg::datamover_regif__in_t 72

Outputs 8

DirNameTypeWidth
out s_cpuif_req_stall_wr logic 1
out s_cpuif_req_stall_rd logic 1
out s_cpuif_rd_ack logic 1
out s_cpuif_rd_err flag logic 1
out s_cpuif_rd_data logic[31:0] 32
out s_cpuif_wr_ack logic 1
out s_cpuif_wr_err flag logic 1
out hwif_out datamover_regif_pkg::datamover_regif__out_t 772

Instantiated by

datamover_ctrl