datamover_top · RTLDoc

Internal connectivity

the submodules of datamover_top and the signals between them

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The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Clocks

clk_i

Resets

rst_niactive-low

Test / DFT

test_mode_i

Ports 7

Inputs 4

Dir	Name	Type	Width
in	clk_i	logic	1
in	rst_ni	logic	1
in	test_mode_i	logic	1
in	periph	hwpe_ctrl_intf_periph .slave	-

Outputs 3

Dir	Name	Type	Width
out	evt_o flag	logic[7:0][1:0]	16
out	busy_o flag	logic	1
out	tcdm	hci_core_intf .initiator	-

Parameters 20

Name	Resolved value
ID	32'd10
BANDWIDTH	32'd576
NUM_ELEM_WORD	32'd8
ELEM_WIDTH	32'd8
N_CORES	32'd8
N_CONTEXT	32'd2
MISALIGNED_ACCESSES	32'd1
EnableIm2col	1'b1
HCI_SIZE_tcdm	224'd36156105996294961723667258600855805061...e23
WORD_WIDTH	32'd64
NUM_WORDS	32'd9
BANDWIDTH_ALIGNED	32'd512
NB_ELEMENTS	32'd64
DEBUG_DW	32'd576
DEBUG_BW	32'd8
DEBUG_AW	32'd32
DEBUG_UW	32'd1
DEBUG_IW	32'd8
DEBUG_EW	32'd1
DEBUG_EHW	32'd1

Submodules 3

Instance	Module	Count	Conns
i_streamer	datamover_streamer	1	10
i_engine	datamover_engine	1	8
i_ctrl	datamover_ctrl	1	9

Interfaces / streams 2

data_inhwpe_stream_intf_stream data_outhwpe_stream_intf_stream

Instantiated by

datamover_top_wrap

Imports

hwpe_ctrl_package::*hci_package::*datamover_package::*