module
datamover_top
4in
3out
3sub
Internal connectivity
the submodules of datamover_top and the signals between themBlue: an input. Magenta: an output. Green: an interface. Orange: no direction. A hexagon shows a port that goes in two directions. The clock and the reset nets are not in the graph.
Clocks
clk_i
Resets
rst_niactive-low
Ports 7
Inputs 4
| Dir | Name | Type | Width |
|---|---|---|---|
| in | clk_i | logic | 1 |
| in | rst_ni | logic | 1 |
| in | test_mode_i | logic | 1 |
| in | periph | hwpe_ctrl_intf_periph .slave | - |
Outputs 3
| Dir | Name | Type | Width |
|---|---|---|---|
| out | evt_o | logic[1:0][1:0] | 4 |
| out | busy_o | logic | 1 |
| out | tcdm | hci_core_intf .initiator | - |
Parameters 19
| Name | Resolved value |
|---|---|
| ID | 32'd4 |
| BANDWIDTH | 32'd512 |
| NUM_ELEM_WORD | 32'd8 |
| ELEM_WIDTH | 32'd8 |
| N_CORES | 32'd2 |
| N_CONTEXT | 32'd2 |
| MISALIGNED_ACCESSES | 32'd0 |
| HCI_SIZE_tcdm | 224'h0 |
| WORD_WIDTH | 32'd64 |
| NUM_WORDS | 32'd8 |
| BANDWIDTH_ALIGNED | 32'd512 |
| NB_ELEMENTS | 32'd64 |
| DEBUG_DW | 32'd0 |
| DEBUG_BW | 32'd0 |
| DEBUG_AW | 32'd0 |
| DEBUG_UW | 32'd0 |
| DEBUG_IW | 32'd0 |
| DEBUG_EW | 32'd0 |
| DEBUG_EHW | 32'd0 |
Submodules 3
| Instance | Module | Count | Conns |
|---|---|---|---|
| i_streamer | datamover_streamer | 1 | 10 |
| i_engine | datamover_engine | 1 | 8 |
| i_ctrl | datamover_ctrl | 1 | 9 |
Interfaces / streams 2
data_inhwpe_stream_intf_stream
data_outhwpe_stream_intf_stream
Instantiated by
Imports
hwpe_ctrl_package::*hci_package::*datamover_package::*