module

hwpe_stream_fifo

hwpe-stream.bender/git/checkouts/hwpe-stream-d7752ab5ca8011c5/rtl/fifo/hwpe_stream_fifo.sv:68elaboratedas datamover_top_wrap.i_datamover_top.i_streamer.i_source.nopassthrough_gen.i_fifo_addr

4in

2out

0sub

The hwpe_stream_fifo module implements a hardware FIFO queue for HWPE-Stream streams, used to withstand data scarcity (valid`=0) or backpressure (`ready`=0), decoupling two architectural domains. This FIFO is single-clock and therefore cannot be used to cross two distinct clock domains. The FIFO will lower its `ready signal on the input stream push_i interface when it is completely full, and will lower its valid signal on the output stream pop_o interface when it is completely empty. The regular FIFO does not allow for transactions to fall through the FIFO queue if there are no stalls, therefore any transaction always "pays" at least 1 cycle latency through the FIFO. The alternative is the passthrough FIFO hwpe_stream_fifo_passthrough.

`hwpe_stream_fifo` design-time parameters.
Name	Default	Description
DATA_WIDTH	32	Width of the HWPE-Streams (typically multiple of 32, but this module does not care).
FIFO_DEPTH	8	Depth of the FIFO queue (multiple of 2).
LATCH_FIFO	0	If 1, use latches instead of flip-flops (requires special constraints in synthesis).
LATCH_FIFO_TEST_WRAP	0	If 1 and LATCH_FIFO is 1, wrap latches with BIST wrappers.

`hwpe_stream_fifo` output flags.
Name	Type	Description
empty	logic	1 if the FIFO is currently empty.
full	logic	1 if the FIFO is currently full.
push_pointer	logic[7:0]	Unused.
pop_pointer	logic[7:0]	Unused.

Interface

the boundary of hwpe_stream_fifo — it instantiates no other module

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The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Clocks

clk_i

Resets

rst_niactive-low

Clears

clear_isynchronous

Ports 6

Inputs 4

Dir	Name	Type	Width
in	clk_i	logic	1
in	rst_ni	logic	1
in	clear_i	logic	1
in	push_i	hwpe_stream_intf_stream .sink	-

Outputs 2

Dir	Name	Type	Width
out	flags_o flag	hwpe_stream_package::flags_fifo_t	20
out	pop_o	hwpe_stream_intf_stream .source	-

Parameters 8

Name	Resolved value
DATA_WIDTH	32'd36
ELEMENT_WIDTH	32'd8
FIFO_DEPTH	32'd2
LATCH_FIFO	32'd0
LATCH_FIFO_TEST_WRAP	32'd0
STRB_WIDTH	32'd4
DATA_STRB_WIDTH	32'd40
ADDR_DEPTH	1

Instantiated by

datamover_engine hci_core_fifo hci_core_sink hci_core_source