module
fifo_v3
7in
4out
0sub
Interface
the boundary of fifo_v3 — it instantiates no other moduleThe ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.
Clocks
clk_i
Resets
rst_niactive-low
Test / DFT
testmode_i
Ports 11
Inputs 7
| Dir | Name | Type | Width |
|---|---|---|---|
| in | clk_i | logic | 1 |
| in | rst_ni | logic | 1 |
| in | flush_i ctrl | logic | 1 |
| in | testmode_i | logic | 1 |
| in | data_i | fifo_v3.dtype | 553 |
| in | push_i | logic | 1 |
| in | pop_i | logic | 1 |
Outputs 4
| Dir | Name | Type | Width |
|---|---|---|---|
| out | full_o | logic | 1 |
| out | empty_o | logic | 1 |
| out | usage_o | logic[0:0] | 1 |
| out | data_o | fifo_v3.dtype | 553 |
Parameters 6
| Name | Resolved value |
|---|---|
| FALL_THROUGH | 1'b0 |
| DATA_WIDTH | 32'd32 |
| DEPTH | 32'd2 |
| dtype | - |
| ADDR_DEPTH | 32'd1 |
| FifoDepth | 32'd2 |