module
datamover_streamer
7in
3out
4sub
Internal connectivity
the submodules of datamover_streamer and the signals between themBlue: an input. Magenta: an output. Green: an interface. Orange: no direction. A hexagon shows a port that goes in two directions. The clock and the reset nets are not in the graph.
Clocks
clk_i
Resets
rst_niactive-low
Ports 10
Inputs 7
| Dir | Name | Type | Width |
|---|---|---|---|
| in | clk_i | logic | 1 |
| in | rst_ni | logic | 1 |
| in | test_mode_i | logic | 1 |
| in | enable_i | logic | 1 |
| in | clear_i | logic | 1 |
| in | data_out | hwpe_stream_intf_stream .sink | - |
| in | ctrl_i | datamover_package::ctrl_streamer_t | 906 |
Outputs 3
| Dir | Name | Type | Width |
|---|---|---|---|
| out | data_in | hwpe_stream_intf_stream .source | - |
| out | tcdm | hci_core_intf .initiator | - |
| out | flags_o | datamover_package::flags_streamer_t | 9 |
Parameters 12
| Name | Resolved value |
|---|---|
| BANDWIDTH | 32'd32 |
| NUM_ELEM_WORD | 32'd4 |
| ELEM_WIDTH | 32'd8 |
| TCDM_FIFO_DEPTH | 32'd2 |
| MISALIGNED_ACCESSES | 32'd1 |
| HCI_SIZE_tcdm | 224'h0 |
| BW | 32'd0 |
| AW | 32'd0 |
| UW | 32'd0 |
| IW | 32'd0 |
| EW | 32'd0 |
| EHW | 32'd0 |
Submodules 4
| Instance | Module | Count | Conns |
|---|---|---|---|
| i_source | hci_core_source | 1 | 9 |
| i_sink | hci_core_sink | 1 | 9 |
| i_tcdm_fifo | hci_core_fifo | 1 | 6 |
| i_tcdm_filter | hci_core_r_valid_filter | 1 | 6 |
Interfaces / streams 3
Instantiated by
Imports
hwpe_stream_package::*hci_package::*datamover_package::*