RTLDoc datamover (lkesting/konark) - RTLDoc example
datamover (lkesting/konark) - RTLDoc example › datamover › datamover_streamer
module

datamover_streamer

datamover rtl/datamover_streamer.sv:22 elaboratedas datamover_top_wrap.i_datamover_top.i_streamer
7in
3out
4sub

Internal connectivity

the submodules of datamover_streamer and the signals between them
G cluster_datamover_streamer datamover_streamer cluster_gen_dont_use_fifo_gen dont_use_fifo_gen p__ctrl_i ctrl_i i__i_source i_source hci_core_source i__i_sink i_sink hci_core_sink i__i_tcdm_filter i_tcdm_filter hci_core_r_valid_filter i__i_ld_st_mux_static i_ld_st_mux_static hci_core_mux_dynamic l__logic internal logic of datamover_streamer n__tcdm_prefilter tcdm_prefilter n__virt_tcdm virt_tcdm p__data_out data_out p__ctrl_i->i__i_source p__ctrl_i->i__i_sink p__enable_i enable_i p__data_out->i__i_sink sink p__enable_i->l__logic p__data_in data_in p__flags_o flags_o p__tcdm tcdm i__i_source->p__data_in source i__i_source->p__flags_o i__i_source->n__virt_tcdm initiator i__i_sink->p__flags_o i__i_sink->n__virt_tcdm initiator i__i_tcdm_filter->p__tcdm initiator i__i_ld_st_mux_static->n__tcdm_prefilter initiator n__tcdm_prefilter->i__i_tcdm_filter target n__virt_tcdm->i__i_ld_st_mux_static target
scroll or pinch to zoom · drag to move · click a node to open

The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Clocks

clk_i

Resets

rst_niactive-low

Clears

clear_isynchronous

Test / DFT

test_mode_i

Ports 10

Inputs 7

DirNameTypeWidth
in clk_i logic 1
in rst_ni logic 1
in test_mode_i logic 1
in enable_i ctrl logic 1
in clear_i logic 1
in data_out hwpe_stream_intf_stream .sink -
in ctrl_i ctrl datamover_package::ctrl_streamer_t 1306

Outputs 3

DirNameTypeWidth
out data_in hwpe_stream_intf_stream .source -
out tcdm hci_core_intf .initiator -
out flags_o flag datamover_package::flags_streamer_t 9

Parameters 13

NameResolved value
BANDWIDTH32'd576
NUM_ELEM_WORD32'd8
ELEM_WIDTH32'd8
TCDM_FIFO_DEPTH32'd0
MISALIGNED_ACCESSES32'd1
HCI_SIZE_tcdm224'd36156105996294961723667258600855805061...e23
TRANS_CNT32'd24
BW32'd8
AW32'd32
UW32'd1
IW32'd8
EW32'd1
EHW32'd1

Submodules 4

InstanceModuleCountConns
i_source hci_core_source 1 9
i_sink hci_core_sink 1 9
i_ld_st_mux_static hci_core_mux_dynamic 1 5
i_tcdm_filter hci_core_r_valid_filter 1 6

Interfaces / streams 3

virt_tcdm x2hci_core_intf tcdm_prefifohci_core_intf tcdm_prefilterhci_core_intf

Instantiated by

datamover_top

Imports

hwpe_stream_package::*hci_package::*datamover_package::*