module

datamover_im2col

datamover rtl/datamover_im2col.sv:31 elaboratedas datamover_top_wrap.i_datamover_top.i_engine.gen_im2col.i_im2col

7in

3out

1sub

im2col unit. Every output beat holds NB_ELEMENTS output pixels of one tap.

conv_stride 1: the input is (C x pixels) in NB_ELEMENTS-pixel blocks with image rows of W pixels, W a power of two from 8 to NB_ELEMENTS. The unit keeps the previous and the current block row and reads the next one from the input stream. Per block row it emits the 9 taps of a 3x3 kernel with a 1-pixel zero border.

conv_stride 2: every input beat gives NB_ELEMENTS/2 output pixels, the even input columns. Two beats merge into one output beat.

Internal connectivity

the submodules of datamover_im2col and the signals between them

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The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Clocks

clk_i

Resets

rst_niactive-low

Clears

clear_isynchronous

Ports 10

Inputs 7

Dir	Name	Type	Width
in	clk_i	logic	1
in	rst_ni	logic	1
in	clear_i	logic	1
in	ctrl_i ctrl	datamover_package::ctrl_engine_t	88
in	data_i	logic[63:0][7:0]	512
in	valid_i	logic	1
in	ready_i	logic	1

Outputs 3

Dir	Name	Type	Width
out	ready_o	logic	1
out	data_o	logic[63:0][7:0]	512
out	valid_o	logic	1

Parameters 5

Name	Resolved value
NB_ELEMENTS	32'd64
ELEM_WIDTH	32'd8
NB_ELEM_LOG2	32'd6
LOG2W_MIN	32'd3
NUM_W	32'd4

Submodules 1

Instance	Module	Count	Conns
i_out_reg	stream_register	1	10

Instantiated by

datamover_engine

Imports

datamover_package::*