interface
hci_core_intf
1in
0out
0sub
Signals 21
the wires that the two sides of this interface share
| Name | Type | Width |
|---|---|---|
| req | logic | 1 |
| gnt | logic | 1 |
| r_valid | logic | 1 |
| r_ready | logic | 1 |
| add | logic[31:0] | 32 |
| wen | logic | 1 |
| data | logic[575:0] | 576 |
| be | logic[71:0] | 72 |
| user | logic[0:0] | 1 |
| id | logic[7:0] | 8 |
| r_data | logic[575:0] | 576 |
| r_user | logic[0:0] | 1 |
| r_id | logic[7:0] | 8 |
| r_opc | logic | 1 |
| ecc | logic[0:0] | 1 |
| r_ecc | logic[0:0] | 1 |
| ereq | logic[0:0] | 1 |
| egnt | logic[0:0] | 1 |
| r_evalid | logic[0:0] | 1 |
| r_eready | logic[0:0] | 1 |
| clk_assert | logic | 1 |
Modports 3
each side of the interface, with the direction of each signal from that side
| Modport | Drives | Reads |
|---|---|---|
| initiator | req, add, wen, data, be, r_ready, user, id, ecc, ereq, r_eready | gnt, r_data, r_valid, r_user, r_id, r_opc, r_ecc, egnt, r_evalid |
| target | gnt, r_data, r_valid, r_user, r_id, r_opc, r_ecc, egnt, r_evalid | req, add, wen, data, be, r_ready, user, id, ecc, ereq, r_eready |
| monitor | req, gnt, add, wen, data, be, r_ready, user, id, r_data, r_valid, r_user, r_id, r_opc, ecc, r_ecc, ereq, egnt, r_evalid, r_eready |
Clocks
clk
Ports 1
Inputs 1
| Dir | Name | Type | Width |
|---|---|---|---|
| in | clk | logic | 1 |
Parameters 11
| Name | Resolved value |
|---|---|
| WAIVE_RQ3_ASSERT | 1'b0 |
| WAIVE_RQ4_ASSERT | 1'b0 |
| WAIVE_RSP3_ASSERT | 1'b0 |
| WAIVE_RSP5_ASSERT | 1'b0 |
| DW | 32'd576 |
| AW | 32'd32 |
| BW | 32'd8 |
| UW | 32'd1 |
| IW | 32'd8 |
| EW | 32'd1 |
| EHW | 32'd1 |
Imports
hci_package::*