datamover_top_wrap

A wrapper for datamover_top that unrolls the interfaces to HCI and the peripheral slave interconnect, making it possible to manually connect the desired ports

Internal connectivity

the submodules of datamover_top_wrap and the signals between them

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The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Clocks

clk_i

Resets

rst_niactive-low

Test / DFT

test_mode_i

Ports 23

Inputs 12

Dir	Name	Type	Width
in	clk_i	logic	1
in	rst_ni	logic	1
in	test_mode_i	logic	1
in	tcdm_gnt	logic[8:0]	9
in	tcdm_r_data	logic[8:0][63:0]	576
in	tcdm_r_valid	logic[8:0]	9
in	periph_req	logic	1
in	periph_add	logic[31:0]	32
in	periph_wen	logic	1
in	periph_be	logic[3:0]	4
in	periph_data	logic[31:0]	32
in	periph_id	logic[9:0]	10

Outputs 11

Dir	Name	Type	Width
out	evt_o flag	logic[7:0][1:0]	16
out	busy_o flag	logic	1
out	tcdm_req	logic[8:0]	9
out	tcdm_add	logic[8:0][31:0]	288
out	tcdm_wen	logic[8:0]	9
out	tcdm_be	logic[8:0][7:0]	72
out	tcdm_data	logic[8:0][63:0]	576
out	periph_gnt	logic	1
out	periph_r_data	logic[31:0]	32
out	periph_r_valid	logic	1
out	periph_r_id	logic[9:0]	10

Parameters 23

Name	Resolved value
WAIVE_RQ3_ASSERT	1'b0
WAIVE_RQ4_ASSERT	1'b0
WAIVE_RSP3_ASSERT	1'b0
WAIVE_RSP5_ASSERT	1'b0
ADDR_WIDTH	32'd32
ID	32'd10
BANDWIDTH	32'd576
NUM_ELEM_WORD	32'd8
ELEM_WIDTH	32'd8
N_CORES	32'd8
N_CONTEXT	32'd2
MISALIGNED_ACCESSES	32'd1
EnableIm2col	1'b1
WORD_WIDTH	32'd64
NUM_WORDS	32'd9
HCI_SIZE_tcdm	224'd36156105996294961723667258600855805061...e23
DEBUG_DW	32'd576
DEBUG_BW	32'd8
DEBUG_AW	32'd32
DEBUG_UW	32'd1
DEBUG_IW	32'd8
DEBUG_EW	32'd1
DEBUG_EHW	32'd1

Submodules 1

Instance	Module	Count	Conns
i_datamover_top	datamover_top	1	7

Interfaces / streams 2

tcdmhci_core_intf periphhwpe_ctrl_intf_periph

Imports

hwpe_ctrl_package::*hci_package::*datamover_package::*