module

datamover_engine

datamover rtl/datamover_engine.sv:22 elaboratedas datamover_top_wrap.i_datamover_top.i_engine

7in

1out

4sub

Internal connectivity

the submodules of datamover_engine and the signals between them

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The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Clocks

clk_i

Resets

rst_niactive-low

Clears

clear_isynchronous

Test / DFT

test_mode_i

Ports 8

Inputs 7

Dir	Name	Type	Width
in	clk_i	logic	1
in	rst_ni	logic	1
in	test_mode_i	logic	1
in	enable_i ctrl	logic	1
in	clear_i	logic	1
in	ctrl_i ctrl	datamover_package::ctrl_engine_t	88
in	data_in	hwpe_stream_intf_stream .sink	-

Outputs 1

Dir	Name	Type	Width
out	data_out	hwpe_stream_intf_stream .source	-

Parameters 14

Name	Resolved value
FIFO_DEPTH	32'd2
EnableIm2col	1'b1
BANDWIDTH_ALIGNED	32'd512
NUM_ELEM_WORD	32'd8
ELEM_WIDTH	32'd8
WORD_WIDTH	32'd64
NB_ELEMENTS	32'd64
NB_ELEM_LOG2	32'd6
TILE_CNT_WIDTH	32'd11
ELEM_CNT_WIDTH	32'd17
ACCESS_CNT_BASE	32'd22
ACCESS_CNT_WIDTH	32'd24
STRB_ONE	64'h1
MAX_SHIFTING	32'd8

Submodules 4

Instance	Module	Count	Conns
i_fifo_in	hwpe_stream_fifo	1	6
i_fifo_out	hwpe_stream_fifo	1	6
i_im2col	datamover_im2col	1	10
i_buffer	datamover_buffer	1	7

Interfaces / streams 2

data_in_postfifohwpe_stream_intf_stream data_out_prefifohwpe_stream_intf_stream

Instantiated by

datamover_top

Imports

hwpe_stream_package::*hci_package::*datamover_package::*