module
datamover_engine
7in
1out
4sub
Internal connectivity
the submodules of datamover_engine and the signals between themBlue: an input. Magenta: an output. Green: an interface. Orange: no direction. A hexagon shows a port that goes in two directions. The clock and the reset nets are not in the graph.
Clocks
clk_i
Resets
rst_niactive-low
Ports 8
Inputs 7
| Dir | Name | Type | Width |
|---|---|---|---|
| in | clk_i | logic | 1 |
| in | rst_ni | logic | 1 |
| in | test_mode_i | logic | 1 |
| in | enable_i | logic | 1 |
| in | clear_i | logic | 1 |
| in | ctrl_i | datamover_package::ctrl_engine_t | 97 |
| in | data_in | hwpe_stream_intf_stream .sink | - |
Outputs 1
| Dir | Name | Type | Width |
|---|---|---|---|
| out | data_out | hwpe_stream_intf_stream .source | - |
Parameters 13
| Name | Resolved value |
|---|---|
| FIFO_DEPTH | 32'd2 |
| BANDWIDTH_ALIGNED | 32'd512 |
| NUM_ELEM_WORD | 32'd4 |
| ELEM_WIDTH | 32'd8 |
| WORD_WIDTH | 32'd32 |
| NB_ELEMENTS | 32'd64 |
| NB_ELEM_LOG2 | 32'd6 |
| TILE_CNT_WIDTH | 32'd11 |
| ELEM_CNT_WIDTH | 32'd17 |
| ACCESS_CNT_BASE | 32'd22 |
| ACCESS_CNT_WIDTH | 32'd24 |
| STRB_ONE | 64'h1 |
| MAX_SHIFTING | 32'd4 |
Submodules 4
| Instance | Module | Count | Conns |
|---|---|---|---|
| i_fifo_in | hwpe_stream_fifo | 1 | 6 |
| i_fifo_out | hwpe_stream_fifo | 1 | 6 |
| i_im2col_ctrl | datamover_im2col_ctrl | 1 | 11 |
| i_buffer | datamover_buffer | 1 | 7 |
Interfaces / streams 2
data_in_postfifohwpe_stream_intf_stream
data_out_prefifohwpe_stream_intf_stream
Instantiated by
Imports
hwpe_stream_package::*hci_package::*datamover_package::*