RTLDoc datamover (lkesting/konark) - RTLDoc example
Bender package

datamover

22
modules
8
in datamover
1
design tops
14
dependencies

Design tops

No other module of datamover instantiates these modules.

G cluster_datamover_top_wrap datamover_top_wrap p__busy_o busy_o p__evt_o evt_o i__i_datamover_top i_datamover_top datamover_top i__i_datamover_top->p__busy_o i__i_datamover_top->p__evt_o
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The ports stand at the walls of the module frame: input, left · output, right · interface — a slanted green box is a stream or a bus; the wide green line carries its data, and the arrow gives the direction · control — the dashed amber line shows which module controls what · flag / status · no direction. A straight box is a module. A hexagon is a port that goes in two directions. A dashed inner box is a generate block. The dashed white node is the logic of the module itself: the processes that drive or read a control net. The clock, reset, clear and test-mode nets are not in the graph; the chips below the diagram give them.

Hierarchy

full graph →
G datamover_buffer datamover_buffer datamover_ctrl datamover_ctrl datamover_regif datamover_regif datamover_ctrl->datamover_regif hwpe_ctrl_target hwpe_ctrl_target datamover_ctrl->hwpe_ctrl_target datamover_engine datamover_engine datamover_engine->datamover_buffer datamover_im2col datamover_im2col datamover_engine->datamover_im2col hwpe_stream_fifo hwpe_stream_fifo datamover_engine->hwpe_stream_fifo stream_register stream_register datamover_im2col->stream_register datamover_streamer datamover_streamer hci_core_mux_dynamic hci_core_mux_dynamic datamover_streamer->hci_core_mux_dynamic hci_core_r_valid_filter hci_core_r_valid_filter datamover_streamer->hci_core_r_valid_filter hci_core_sink hci_core_sink datamover_streamer->hci_core_sink hci_core_source hci_core_source datamover_streamer->hci_core_source datamover_top datamover_top datamover_top->datamover_ctrl datamover_top->datamover_engine datamover_top->datamover_streamer datamover_top_wrap datamover_top_wrap datamover_top_wrap->datamover_top fifo_v3 fifo_v3 hci_core_assign hci_core_assign hci_core_sink->hci_core_assign hwpe_stream_addressgen_v4 hwpe_stream_addressgen_v4 hci_core_sink->hwpe_stream_addressgen_v4 hci_core_sink->hwpe_stream_fifo hci_core_source->hwpe_stream_addressgen_v4 hci_core_source->hwpe_stream_fifo hwpe_ctrl_target->fifo_v3
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